Complementary metal-oxide-silicon (CMOS) based integrated circuits utilize p-channel field effect transistors (PFETs) and n-channel field effect transistors (NFETs). Many integrated circuit designs require the devices (i.e., the PFETs and NFETs) to be placed adjacent to each other, which is accomplished by isolating the PFETs and NFETs with trench isolation. Trench isolation is essentially a dielectric filled trench formed in the silicon substrate that surrounds the perimeter of and electrically isolates the regions of the PFETs and NFETs formed in the silicon substrate from each other.
However, with the ever increasing need for increased device density, the width of the trench isolation between adjacent devices is decreasing and defect free isolation structures are becoming more difficult to fabricate. Accordingly, there exists a need in the art to improve the trench isolation structure and fabrication methodologies to keep pace with the decreasing dimensions of the trench isolation.